FIG. 1 is a circuit diagram of a conventional ferroelectric random access memory (FRAM) cell 10. Referring to FIG. 1, the FRAM cell 10 includes a switching transistor 11 and a ferroelectric capacitor 13 that are connected between a corresponding word line WL and a corresponding bit line BL. A FRAM is a next generation non-volatile memory using the polarization characteristics of ferroelectrics.
A write operation and a read operation are performed on the FRAM cell 10 based on a plate pulse applied to a plate line PL of the ferroelectric capacitor 13.
If a plate pulse is applied to the plate line PL in order to read data (for example, data “1”) stored in the ferroelectric capacitor 13, the data “1” stored in the ferroelectric capacitor 13 is changed to data “0”. Thus, in order to restore the data “1” stored in the ferroelectric capacitor 13 at the end of the read operation, the data “1” is written to the ferroelectric capacitor 13. This operation is called “write-back”.
FIG. 2 is a timing diagram of a normal read operation performed on the conventional FRAM cell 10. Referring to FIGS. 1 and 2, the timing of a normal read operation based on an address signal ADD is largely divided into a charge sharing interval t1, a sensing interval t2, and a write-back interval t3.
In the charge sharing interval t1, charge sharing occurs in response to a plate pulse PPLS and a sense amplifier enable signal SAEN. In the sensing interval t2, data stored in the FRAM cell 10 is sensed by a sense amplifier (not shown). In the write-back interval t3, the original data, specifically, data “1”, which can be damaged during a read operation, is restored (i.e., the read of the cell is destructive).
However, in the write-back interval t3, if a low voltage is applied to the plate line PL at a timing when the data “1” is restored in the FRAM cell 10, a normal write-back operation may not occur such that data stored in the ferroelectric capacitor 13 may be destroyed or changed.